Cloud Server Infrastructure: Perspectives on Hardware and Software from the RISER Project

November 27, 2024, online (CET)

Workshop Agenda

13:00 : Welcome, overview of RISER project and workshop topics (Manolis Marazakis, FORTH)
13:20 : Cloud roadmap for Arm SoCs – speaker: Roberto Mostallino (SiPEARL)
14:00 : RISC-V Server Software Landscape – speaker: Oliver Perks (RISE & Rivos Inc)
14:45 : Tools for RISC-V SoC Bring-up – speaker: Nick Kossifidis (FORTH)
15:15 : Overview of the RISC-V server SoC specification – speaker: Ved Shanbhogue (Rivos Inc)
16:00 : Q&A, Panel (40′)
16:40 : Closing Remarks (5′)

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13:00: Welcome, overview of the RISER project and workshop topics

Speaker: Manolis Marazakis (FORTH)

Manolis Marazakis is a staff research scientist at the Institute of Computer science, FORTH (Greece). His research interests are in architectures and efficient systems software for high-performance servers in data center environments. He is the coordinator of the RISER project.

13:20: Cloud roadmap for Arm SoC

Speaker: Roberto Mostallino (SiPEARL)

Roberto Mostallino works as Product marketing manager at SiPearl, the French company building the European high-performance and low-power microprocessor for HPC and AI workloads. Previously working in the photonics industry, he now leverages his passion for cutting-edge technology to empower and shape the future of HPC with SiPearl’s pioneering solutions. Roberto has completed a PhD in Photonics from Bordeaux University in France and a Master’s degree in Electronics Engineering from Università di Cagliari in Italy.

14:00 : RISC-V Server Software Landscape

Speaker: Dr. Oliver Perks (RISE & Rivos Inc)

In this presentation Rivos will summarize the current state of software readiness for server class RISC-V CPUs. As a founding member of RISC-V Software Ecosystem (RISE), a community effort to enable and grow the RISC-V software ecosystem, we will cover past and current efforts to enhance end user experience on RISC-V, ahead of the wider availability of server class hardware. Attendees will gain insight to the challenges of collaboratively developing open source software for multiple RISC-V implementations, many of which are pre-silicon. How, by working to open standards, with common methodologies we are able to port, and test, a broad range of applications and supporting dependencies. In addition to local compilation any robust ecosystem is dependent on prebuilt packages, and binary distribution. This is especially critical for Python frameworks, which are an increasingly critical component of production software stacks especially for AI/ML workloads. To improve the end user experience RISE has been focusing on Python packaging, providing a Python package index for distributing RISC-V built and qualified packages – to bridge the gap until wider upstream integration. We will also demonstrate the value of package distribution at the operating system level, and our work with leading Linux based providers to improve user experience. Lastly we will present on some of the funding opportunities from RISE for porting software to RISC-V, acknowledging the effort required to build a robust ecosystem.

Oliver Perks is a Software Engineer at Rivos, a RISC-V silicon startup. With a long history of working at the cutting edge of HPC, Oliver has previously worked for the likes of AWS and Arm to port and adopt future architectures. Oliver received his PhD from Warwick University, studying the analysis of memory consumption of HPC applications.

Founded in 2021, Rivos develops industry-leading, power-efficient RISC-V server solutions designed for demanding AI and data analytics workloads. With co-designed optimized CPUs, a Data Parallel Accelerator, and an open software stack. Customer workloads are easily deployed using their existing models giving an immediate TCO benefit. Headquartered in Santa Clara, CA, Rivos is expanding globally and currently recruiting top engineering talent.

14:45: Tools for RISC-V SoC Bring-up

Speaker: Nick Kossifidis (FORTH)

The RISER project aims to build accelerator and microserver systems based on RISC-V SoCs from ongoing European projects funded by the EuroHPC JU. Working with experimental hardware platforms requires substantial effort on verification and bring-up, including bare-metal tests aimed at the core, memory, and platform levels. Booting a full-blown Linux distribution greatly expands test coverage but also complexity. We recommend starting with a bare-minimum kernel configuration, without networking and storage functions, and even opting for a no-MMU system configuration, to progressively expand test coverage. In this talk, we outline the features and limitations of no-MMU and summarize our practical experience in early-stage verification of RISC-V prototype platforms.

Nick Kossifidis is a principal research engineer at the Institute of Computer Science of FORTH (Greece), currently working on the bringup, validation, and optimization process of various RISC-V prototypes. He is the Chair of the RISC-V Runtime Integrity SIG and has multiple contributions in open source projects, including various subsystems of the Linux kernel.

15:15 : Overview of the RISC-V server SoC specification

Speaker: Ved Shanbhogue (Rivos Inc)

The RISC-V server SoC specification aims to enhance software compatibility across the RISC-V server SoCs. This talk will cover key hardware capabilities, including harts, timers, PCIe root complexes, RAS, and management features, and explains how this specification simplifies OS and hypervisor support. Attendees will learn about the collaborative efforts and partnerships driving this initiative and its impact on high-performance server applications.

Ved Shanbhogue is with Rivos Inc. and a key contributor to RISC-V. He has contributed to development of various ratified and in-progress RISC-V ISA (Zawrs, Zacas, Zicfiss, Zicfilp) and non-ISA extensions (IOMMU, CBQRI, Server SoC HW spec., RAS ERI). He chairs the SoC infrastructure HC. Before RIvos he worked for Intel corporation and contributed sever x86 ISA and non-ISA extensions. Ved has more than 150 issued patents and several publications.

16:00 : Q&A, Panel (40′)
16:40 : Closing Remarks (5′)

*Please note: The workshop will be recorded.